View ATF1500A_975059.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* High-density, High-performance Electrically-erasable Complex
Programmable Logic Device - 44-pin, 32 I/O CPLD - 7.5 ns Maximum Pin-to-pin Delay - Registered Operation Up To 125 MHz - Fully Connected Input and Feedback Logic Array - Backward Compatibility with ATF1500/L Software and Hardware Flexible Logic Macrocell - D/T/Latch Configurable Flip Flops - Global and Individual Register Control Signals - Global and Individual Output Enable - Programmable Output Slew Rate Advanced Power Management Features - Automatic 3 mA Stand-By (ATF1500AL) - Pin-controlled 10 mA Standby Mode - Programmable Pin-Keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in 44-pin PLCC and TQFP Packages Advanced Flash Technology - 100% Tested - Completely Reprogrammable - 100 Program/Erase Cycles - 20 Year Data Retention - 2000V ESD Protection - 200 mA Latch-up Immunity Supported By Popular 3rd Party Tools Security Fuse Feature Pin-compatible with the Most Commonly Used Devices
*
*
Highperformance EPLD ATF1500A ATF1500AL
* * *
* * *
Description
The ATF1500A is a high-performance, high-density complex PLD. Built on an advanced Flash technology, it has maximum pin to pin delays of 7.5 ns and supports sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs. The ATF1500A's global input and feedback architecture simplifies logic placement and eliminates pinout changes due to design changes. (continued)
Pin Configurations
Pin Name CLK I I/O GCLR OE1, OE2 VCC PD Function Clock Logic Inputs Bidirectional Buffers Register Reset (active low) Output Enable (active low) +5V Supply Power Down (active high)
I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O
PLCC Top View
I/O I/O I/O/PD VCC OE2/I GCLR/I OE1/I CLK/I GND I/O I/O
TQFP Top View
I/O I/O I/O/PD VCC OE2/I GCLR/I OE1/I CLK/I GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O
18 19 20 21 22 23 24 25 26 27 28
7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30 29
I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O
1 2 3 4 5 6 7 8 9 10 11
I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O
I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O
Rev. 0759E-06/99
1
Functional Logic Diagram(1)
Note:
1.
Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.
The ATF1500A has 32 bi-directional I/O pins and 4 dedicated input pins. Each dedicated input pin can also serve as a global control signal: register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.
Each of the 32 logic macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. Because of this global bussing, each of these signals is always available to all 32 macrocells in the device.
2
ATF1500A(L)
ATF1500A(L)
Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals within a regional bus are connected to all 16 macrocells within the region. Cascade logic between macrocells in the ATF1500A allows fast, efficient generation of complex logic functions. The ATF1500A contains 4 such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms. used to generate buried foldback and cascade logic signals. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file.
Bus Friendly Pin-Keeper Input and I/O's
All Input and I/O pins on the ATF1500A have programmable "pin keeper" circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused Input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Pin-keeper circuits can be disabled. Programming is controlled in the logic design file. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os.
Design Software Support
ATF1500A designs are supported by several 3rd party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.
Input Diagram
VCC
INPUT 100K
ESD PROTECTION CIRCUIT
Speed/Power Management
The ATF1500A has several built-in speed and power management features. The ATF1500A contains circuitry that automatically puts the device into a low power stand-by mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 10 MHz. All ATF1500As also have an optional pin-controlled power down mode. In this mode, current drops to below 10 mA. When the power down option is selected, the PD pin is used to power down the part. The power down option is selected in the design source file. When enabled, the device goes into power down when the PD pin is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD is brought low. When the power down feature is enabled, the PD cannot be used as a logic input or output. However, the PD pin's macrocell may still be
PROGRAMMABLE OPTION
I/O Diagram
VCC
OE
DATA
I/O
VCC
100K
PROGRAMMABLE OPTION
3
ATF1500A(L) Macrocell
ATF1500A Macrocell
The ATF1500A macrocell is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and enable; and logic array inputs. routed to the OR gate, creating a five input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay. The macrocell's XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows output polarity selection. For registered functions, the fixed levels allow De Morgan minimization of the product terms. The XOR gate is also used to emulate T-type flip flops.
Product Terms and Select Mux
Each ATF1500A macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.
Flip Flop
The ATF1500A's flip flop has very flexible data and control functions. The data input can come from either the XOR gate or from a separate product term. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell.
OR/XOR/CASCADE Logic
The ATF1500A macrocell's OR/XOR/CASCADE logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be
4
ATF1500A(L)
ATF1500A(L)
In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can be either the global CLK pin or an individual product term. The flip flop changes state on the clock's rising edge. When the CLK pin is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop's asynchronous reset signal (AR) can be either the pin global clear (GCLR), a product term, or always off. AR can also be a logic OR of GCLR with a product term. The asynchronous preset (AP) can be a product term or always off. The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configuration all the macrocell resources are still available, including the buried feedback, expander and CASCADE logic. The output enable for each macrocell can also be selected as either of the two OE pins or as an individual product term.
Global/Regional Busses
The global bus contains all Input and I/O pin signals as well as the buried feedback signal from all 32 macrocells. Together with the complement of each signal, this provides a 68 bit bus as input to every product term. Having the entire global bus available to each macrocell eliminates any potential routing problems. With this architecture designs can be modified without requiring pinout changes. Each macrocell also generates a foldback product term. This signal goes to the regional bus, and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell's product terms. The 16 foldback terms in each region allow generation of high fan-in sum terms (up to 21 product terms) with a small additional delay.
Output Select and Enable
The ATF1500A macrocell output can be selected as registered or combinatorial. When the output is registered, the same registered signal is fed back internally to the global bus. When the output is combinatorial, the buried feedback can be either the same combinatorial signal or it can be the register output if the separate product term is chosen as the flip flop input.
5
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40C to +85C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 5.25V for pulses of less than 20 ns.
DC and AC Operating Conditions
Commercial Operating Temperature (ambient) VCC Power Supply 0C - 70C 5V 5% Industrial -40C - 85C 5V 10%
DC Characteristics
Symbol IIL IIH Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Condition 0 VIN VIL (Max) VIH, Min VIN VCC Com. ATF1500A ICC1(1) Power Supply Current, Standby VCC = Max, VIN = 0, VCC ATF1500AL Ind. ICC2 Power Supply Current, Pin-Controlled Power Down Mode Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC = Min VCC = Min IOL = 12 mA IOH = -4 mA IOH = -0.2 mA 2.4 VCC - 0.2 VCC = Max, VIN = 0, VCC VOUT = 0.5V VCC, Min < VCC < VCC, Max -0.5 2.0 2 5 10 mA mA Ind. Com. 100 3 mA mA 70 Min Typ Max -10 10 Units A A mA
IOS VIL VIH VOL VOH Note:
-130 0.8 VCC + 1 0.45
mA V V V V V
1. All ICC parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each region.
6
ATF1500A(L)
ATF1500A(L)
AC Waveforms
Register AC Characteristics, Input Pin Clock
-7 Symbol tCOS(1) tCFS tSIS tSFS tHS tPS tWS Parameter Clock to Output Clock to Feedback I, I/O Setup Time Feedback Setup Time Input, I/O, Feedback Hold Time Clock Period Clock Width External Feedback 1/(tSIS + tCOS) FMAXS Internal Feedback 1/(tSFS + tCFS) No Feedback 1/(tPS) tRPRS tRTRS Note: Reset Pin Recovery Time Reset Term Recovery Time 2 6 0 6 3 95 125 166.7 3 9 Min Max 4.5 2 6 6 0 8 4 76.9 100 125 3 10 Min 2 -10 Max 5 2 8 8 0 9 4.5 62.5 83.3 111 4 12 Min 2 -12 Max 6 2 10 10 0 10 5 52.6 76.9 100 5 13 Min 2 -15 Max 8 2 11 11 0 11 5.5 43 71 91 5 14 Min 2 -20 Max 9 2 14 12 0 12 6 40 66 83 Min 2 -25 Max 9 2 16 13 Units ns ns ns ns ns ns ns MHz MHz MHz ns ns
1. For slow slew outputs, add tSSO .
7
Register AC Characteristics, Product Term Clock
-7 Symbol tCOA(1) tCFA tSIA tSFA tHA tPA tWA Parameter Clock to Output Clock to Feedback I, I/O Setup Time Feedback Setup Time Input, I/O, Feedback Hold Time Clock Period Clock Width External Feedback 1/(tSIA + tCOA) FMAXA Internal Feedback 1/(tSFA + tCFA) No Feedback 1/(tPA) tRPRA tRTRA Note: Reset Pin Recovery Time Reset Term Recovery Time 0 4 3 3 2 6 3 95.2 125 166.7 0 5 Min Max 7.5 5 3 3 3 8 4 76.9 100 125 0 6 Min -10 Max 10 7 4 4 4 10 5 62.5 90.9 100 0 6 Min -12 Max 12 7 4 4 4 12 6 52.6 76.9 83.3 Min -15 Max 15 9 8 12 5 24 12 38 41.7 41.7 0 7 0 8 Min -20 Max 18 12 10 15 5 30 15 33.3 33.3 33.3 Min -25 Max 20 15 Units ns ns ns ns ns ns ns MHz MHz MHz ns ns
1. For slow slew outputs, add tSSO .
8
ATF1500A(L)
ATF1500A(L)
AC Characteristics
-7 Symbol tPD(1) tPD2 tPD3(1) Parameter I, I/O or FB to Non-Registered Output I, I/O to Feedback Feedback to Non-Registered Output Feedback to Feedback OE Term to Output Enable OE Term to Output Disable OE Pin to Output Enable OE Pin to Output Disable Preset to Feedback Preset to Registered Output Reset Pin to Feedback Reset Pin to Registered Output Reset Term to Feedback Reset Term to Registered Output Cascade Logic Delay Slow Slew Output Adder Foldback Term Delay 1. For slow slew outputs, add tSSO . 2 2 2 1.5 2 Min 2 Max 7.5 5 7.5 3 Min 3 -10 Max 10 7 10 3 Min 3 -12 Max 12 8 12 3 Min 3 -15 Max 15 9 15 3 Min 3 -20 Max 20 12 20 3 Min 3 -25 Max 25 14 25 Units ns ns ns
tPD4 tEA(1) tER tPZX(1) tPXZ tPF tPO(1) tRPF tRPO(1) tRTF tRTO(1) tCAS tSSO tFLD Note:
5 7.5 7.5 5.5 5.5 6 8.5 3 5.5 6 8.5 0.8 3 4 3 2 2 1..5
7 10 10 7 7 9 12 4 7 9 12 0.8 3 5 3 2 2 1.5
8 12 12 8 8 9 14 3 8 9 14 1 3 7 3 2 2 1.5
9 15 15 9 9 12 20 5 11 12 20 1 4 8 3 2 2 1.5
12 20 20 10 10 18 23 5.5 13 15 23 1.5 4 10 3 2 2 1.5
14 25 25 11 11 20 25 6 15 20 25 1.5 4 12
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
9
Power Down AC Characteristics
-7 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV(1) Notes: Parameter Valid I, I/O Before PD High Valid OE(2) Before PD High Valid Clock(2) Before PD High Input Don't Care After PD High OE Don't Care After PD High Clock Don't Care After PD High PD Low to Valid I, I/O PD Low to Valid OE(2) PD Low to Valid Clock(2) PD Low to Valid Output 1. For slow slew outputs, add tSSO . 2. Pin or Product Term. Min 7 7 7 15 15 15 1 1 1 1 Max Min 10 10 10 20 20 20 1 1 1 1 -10 Max Min 12 12 12 22 22 22 1 1 1 1 -12 Max Min 15 15 15 25 25 25 1 1 1 1 -15 Max Min 20 20 20 30 30 30 1 1 1 1 -20 Max Min 25 25 25 35 35 35 1 1 1 1 -25 Max Units ns ns ns ns ns ns s s s s
Input Test Waveforms and Measurement Levels
3.0V AC DRIVING LEVELS 0.0V t r, t f 1.5 ns 1.5V AC MEASUREMENT LEVEL
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25C (1)
Typ CIN COUT Note: 4.5 3.5 Max 5.5 4.5 Units pF pF Conditions VIN = 0V VOUT = 0V
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
10
ATF1500A(L)
ATF1500A(L)
Power Up Reset
The ATF1500A's registers are designed to reset during power up. At a point delayed slightly from V CC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be low on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, from below 0.7 volt, 2. After reset occurs, all input and feedback setup times must be met before driving the clock signal high, and 3. Signals from which clocks are derived must remain stable during tPR. preload mode is enabled by raising an input pin to a high voltage level. Contact Atmel PLD Applications for PRELOAD pin assignments, timing and voltage requirements.
Power Down Mode
The ATF1500A includes an optional pin controlled power down feature. When this mode is enabled, the PD pin acts as the power down pin. When the PD pin is high, the device supply current is reduced to less than 10 mA. During power down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs which were in a HI-Z state at the onset of power down will remain at HI-Z. During power down, all input signals except the power down pin are blocked. Input and I/O hold latches remain active to insure that pins do not float to indeterminate levels, further reducing system power. The power down pin feature is enabled in the logic design file. Designs using the power down pin may not use the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs.
Parameter tPR
Description Power-Up Reset Time Power-Up Reset Voltage
Typ 2
Max 10
Units s
VRST
3.8
4.5
V
Output Slew Rate Control
Each ATF1500A macrocell contains a configuration bit for each I/O to control its output slew rate. This allows selected data paths to operate at maximum throughput while reducing system noise from outputs that are not speed-critical. Outputs default to slow edges, and may be individually set to fast in the design file. Output transition times for outputs configured as "slow" have a tSSO delay adder.
Register Preload
The ATF1500A's registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with preload vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically when vectors are run by any approved programmers. The
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1500A fuse patterns. Once programmed, fuse verify and preload are prohibited. However, the 160-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate.
11
NORMALIZED SUPPLY CURRENT vs. INPUT FREQUENCY ATF1500A (Vcc = 5V, TA = 25C)
SUPPLY CURRENT vs. FREQUENCY ATF1500AL (VCC = 5V, TA = 25C)
ICC
ICC mA
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE ATF1500 (TA = 25C)
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ATF1500 (VCC = 5V)
ICC
ICC mA
OUTPUT SOURCE CURRENT vs. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25C)
OUTPUT SINK SURRENT vs. SUPPLY VOLTAGE (TA = 25C, VOL = 0.45V)
IOH
IOL mA
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE (VOH = 2.4V, TA = 25C)
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE (VCC = 5V, TA = 25C)
IOH mA
IOH mA
12
ATF1500A(L)
ATF1500A(L)
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE (VCC = 5V, TA = 25C)
NORMALIZED tPD vs. AMBIENT TEMPERATURE (VCC = 5V)
IOL mA
tPD
INPUT CLAMP CURRENT vs. INPUT VOLTAGE
NORMALIZED tCOS vs. AMBIENT TEMPERATURE (VCC = 5V)
tCOS
INPUT CURRENT vs. INPUT VOLTAGE (VCC = 5V, TA = 25C)
NORMALIZED tCOA vs. AMBIENT TEMPERATURE (VCC = 5V)
tCOA
NORMALIZED tCOS vs. SUPPLY VOLTAGE (TA = 25C)
tCOS
13
NORMALIZED tSIS vs. SUPPLY VOLTAGE (TA = 25C)
NORMALIZED tSIS vs. AMBIENT TEMPERATURE (VCC = 5V)
tSIS
tSIS
NORMALIZED tSIA vs. SUPPLY VOLTAGE (TA = 25C)
NORMALIZED tSIA vs. AMBIENT TEMPERATURE (VCC = 5V)
tSIA
tSIA
14
ATF1500A(L)
ATF1500A(L)
Ordering Information
tPD (ns) 7.5 10 tCOS (ns) 4.5 5 FMAX (MHz) 95 76.9 Ordering Code ATF1500A-7AC ATF1500A-7JC ATF1500A-10AC ATF1500A-10JC ATF1500A-10AI ATF1500A-10JI 12 6 62.5 ATF1500A-12AC ATF1500A-12JC ATF1500A-12AI ATF1500A-12JI 15 8 52.6 ATF1500A-15AC ATF1500A-15JC ATF1500A-15AI ATF1500A-15JI 20 9 40 ATF1500AL-20AC ATF1500AL-20JC ATF1500AL-20AI ATF1500AL-20JI 25 9 43 ATF1500AL-25AC ATF1500AL-25JC ATF1500AL-25AI ATF1500AL-25JI Package 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J Operation Range Commercial (0C to 70C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Using "C" Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the "I" to the "C" device (7 ns "C" = 10 ns "I") and de-rate power by 30%.
Package Type 44A 44J 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC)
15
Packaging Information
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
PIN 1 ID
12.21(0.478) SQ 11.75(0.458)
.045(1.14) X 45
PIN NO. 1 IDENTIFY
.045(1.14) X 30 - 45
.012(.305) .008(.203)
0.80(0.031) BSC
0.45(0.018) 0.30(0.012)
.656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4)
.630(16.0) .590(15.0) .021(.533) .013(.330)
.050(1.27) TYP .500(12.7) REF SQ
10.10(0.394) SQ 9.90(0.386) 0 7 1.20(0.047) MAX
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
0.20(.008) 0.09(.003)
.022(.559) X 45 MAX (3X)
0.75(0.030) 0.45(0.018)
0.15(0.006) 0.05(0.002)
*Controlling dimension: millimeters
16
ATF1500A(L)
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600
Atmel Operations
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759
Europe
Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697
Atmel Rousset
Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001
Asia
Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369
Japan
Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581
Fax-on-Demand
North America: 1-(800) 292-8635 International: 1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
(c) Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Marks bearing
(R)
and/or
TM
are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper.
0759E-06/99/xM
Terms and product names in this document may be trademarks of others.

▲Up To Search▲

Price & Availability of ATF1500A

	To Download ATF1500A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .